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Integrated Circuit Systems, Inc.
ICS9250-37
Preliminary Product Preview
Frequency Generator for P4TM
Recommended Application: Intel Tehema Chipset Output Features: * 4 Differential CPU Clock Pairs @ 3.3V * 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) * 4 - 66MHz reference output * 10 - 3V 33MHz PCI clocks * 2 - 48MHz clocks * 2 - 14.318 reference output Features: * Up to 156MHz frequency support * Support power management: Power Down Mode * Supports Spread Spectrum modulation: 0 to -0.5% down spread and 0.25 center spread. * Uses external 14.318MHz crystal * Select logic for Differential Swing Control, Test mode, Tristate, Power down, Spread Spectrum, limited frequency select, selective clock enable. * External resistor for current reference Key Specifications: * 3V66 Output jitter <300ps * CPU Output Jitter <200ps * MREF Output jitter <250ps
Pin Configuration
GND MULTSEL0/REF0 MULTSEL1/REF1 VDDREF X1 X2 GNDREF PCICLK0 PCICLK1 VDDPCI PCICLK2 PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 **FS2/PCICLK7 GNDPCI **FS3/PCICLK8 SEL100_133#/PCICLK9 VDDPCI SDATA GND48 *FS0/48MHz_0 **FS1/48MHz_1 VDD48 PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDMREF 3VMREF 3VMREF_B GNDMREF SCLK CPUCLKT3 CPUCLKC3 VDDCPU CPUCLKT2 CPUCLKC2 GNDCPU CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GNDCPU I REF VDDA GNDA VDD3V66 3V66-3 3V66-2 GND3V66 GND3V66 3V66-1 3V66-0 VDD3V66
56-Pin 300mil SSOP
* ** This input has a 120K internal pull up to VDD. This input has a 120K internal pull down to GND.
Block Diagram
Frequency Table
SEL 133/100# FS3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 90.00 100.00 100.40 103.00 105.00 108.00 110.00 112.00 115.00 133.33 133.60 136.00 138.00 140.00 142.00 144.00 MRef 45.00 50.00 50.20 51.50 52.50 54.00 55.00 56.00 57.50 66.67 66.80 68.00 69.00 70.00 71.00 72.00 PCI 30.00 33.33 33.47 34.33 35.00 36.00 36.67 37.33 38.33 33.33 33.40 34.00 34.50 35.00 35.50 36.00 3V66 60.00 66.67 66.93 68.67 70.00 72.00 73.33 74.67 76.67 66.67 66.80 68.00 69.00 70.00 71.00 72.00
PLL2
2
48MHz (1:0)
0 0 0
X1 X2
XTAL OSC PLL1 Spread Spectrum
2
REF (1:0)
0 0 0 0 0 0 1 1 1 1 1 1 1
CPU DIVDER
4 4
CPUCLKT (3:0) CPUCLKC (3:0)
3VMREF DIVDER
3VMREF 3VMREF_B
PD# MULTSEL (1:0)] SEL100/133# FS (3:0) SCLK SDATA
Control Logic Config. Reg.
3V66 DIVDER
4
PCI DIVDER
10
PCICLK (9:0)
3V66 (3:0)
9250-37 Rev A 04/11/01 Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9250-37
ICS9250-37
Preliminary Product Preview
General Description
The ICS9250-37 is a single chip clock solution, for multi processor server or high-end desktop applications. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-37 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Power Groups
VDDREF, GNDREF= REF, X1, X2 VDDPCI, GNDPCI = PCICLK VDD48, GND48 = 48MHz, Fixed PLL2 VDD3V66, GND3V66=3V66 VDDCPU, GNDCPU = CPUCLK VDDMREF, GNDMREF=3VMREF, 3VMREF_B VDDA=VDD (core supply voltage 3.3V)
Pin Configuration
PIN NUMBER
1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53 3, 2 4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56 5 6 17, 15, 14, 12, 11, 9, 8 18 20 21 23 26, 25 28 35, 24, 31, 30 39 51, 48, 45, 42 50, 47, 44, 41 52 54 55
PIN NAME
GND REF/MULTSEL (1:0) VDD X1 X2 PCICLK (6:0) FS21,3 PCICLK7 FS3
1
TYPE
PWR IN PWR X2 Crystal Input
DESCRIPTION
Ground pins for 3.3V supply MULTSEL0 and MULTSEL1 inputs are sensed on power-up and then internally latched prior to the pin being used for output on 3V 14.318MHz clocks. 3.3V power supply 14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output OUT IN OUT IN OUT IN OUT I/O
1,2
PCI clock outputs Margin testing frequency select pin PCI clock output Margin testing frequency select pin PCI clock output CPU Frequency Select. Low=100MHz, High=133MHz PCI clock output Data pin for I2C circuitry 5V tolerant Frequency select pins 48MHz clock output Invokes power-down mode. Active Low. 66MHz reference clocks This pin establishes the reference current for the CPUCLK pairs. This pin takes a fixed precision resistor tied to ground in order to establish the required current. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Clock pin of I2C circuitry 5V tolerant 3V reference to memory clock driver (out of phase with 3Vmref) 3V reference to memory clock driver
PCICLK8 SEL100/133 PCICLK9 SDATA FS1 , FS0 48MHz PD# 3V66 (3:0) I REF CPUCLKT (3:0) CPUCLKC (3:0) SCLK 3VMREF_B 3VMREF
1,3,
IN OUT IN OUT OUT OUT OUT IN OUT OUT
Notes: 1. To ensure proper Intel defined frequency is used, an external 10K ohm pull down resistor is recommended. 2. This input has 120K pull up. 3. This input has 120K pull down.
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2
ICS9250-37
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D2(H ) Dummy Command Code A CK Dummy Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK Byte 7 A CK Stop Bit ICS (Sla ve/Re ceiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controlle r (Host) Start Bit Address D3(H ) ICS (Slave/Rece ive r)
A CK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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3
ICS9250-37
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description Bit2 Bit7 Bit6 Bit5 Bit4 CPU Mref SEL_133/100# FS3 FS3 FS1 FS0 0 0 0 0 0 90.00 45.00 0 0 0 0 1 100.00 50.00 0 0 0 1 0 100.40 50.20 0 0 0 1 1 103.00 51.50 0 0 1 0 0 105.00 52.50 0 0 1 0 1 108.00 54.00 0 0 1 1 0 110.00 55.00 0 0 1 1 1 112.00 56.00 0 1 0 0 0 115.00 57.50 0 1 0 0 1 118.00 59.00 0 1 0 1 0 120.00 60.00 0 1 0 1 1 122.00 61.00 0 1 1 0 0 125.00 62.50 0 1 1 0 1 125.00 62.50 0 1 1 1 0 130.00 65.00 Bit 2, 0 1 1 1 1 133.60 66.80 Bit 7:4 1 0 0 0 0 120.00 60.00 1 0 0 0 1 133.33 66.67 1 0 0 1 0 133.60 66.80 1 0 0 1 1 136.00 68.00 1 0 1 0 0 138.00 69.00 1 0 1 0 1 140.00 70.00 1 0 1 1 0 142.00 71.00 1 0 1 1 1 144.00 72.00 1 1 0 0 0 145.00 72.50 1 1 0 0 1 148.00 74.00 1 1 0 1 0 150.00 75.00 1 1 0 1 1 152.00 76.00 1 1 1 0 0 154.00 77.00 1 1 1 0 1 156.00 78.00 1 1 1 1 0 133.00 66.50 1 1 1 1 1 150.00 75.00 0 - Frequency is selected by hardware select, Latched Input Bit 3 1 - I2C select 0 - Spread Spectrum Disable Bit 1 1 - Spread Spectrum Enabled 0 - Running Bit 0 1- Tristate all outputs Bit PWD PCI 30.00 33.33 33.47 34.33 35.00 36.00 36.67 37.33 38.33 39.33 40.00 40.67 41.67 41.67 43.33 44.53 30.00 33.33 33.40 34.00 34.50 35.00 35.50 36.00 36.25 37.00 37.50 38.00 38.50 39.00 26.60 30.00 3V66 60.00 66.67 66.93 68.67 70.00 72.00 73.33 74.67 76.67 78.67 80.00 81.33 83.33 83.33 86.67 89.07 60.00 66.67 66.80 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 53.20 60.00 Spread Precentage 0 to 0.5% down spread 0 to 0.5% down spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0 to 0.5% down spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread 0.25% center spread
Note1 00000
0 0 0
Note: PWD = Power-Up Default
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ICS9250-37
Preliminary Product Preview
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD 1 1 1 1 50,51 1 47,48 1 44/41 1 41/42 1
DESCRIPTION Readback FS0# Readback FS1# Readback FS2# Readback (SEL133/100#)# CPUC3/T3 CPUC2/T2 CPUC1/T1 CPUC0/T0
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 18 17 15 14 12 11 9 8
PWD 1 1 1 1 1 1 1 1
DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: REF, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: 3V66, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
21 20 54 55 3 2 26 25
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK9 PCICLK8 3VMREF_B 3VMREF REF1 REF0 48MHz_1 48MHz_0
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 35 1 Bit 2 34 1 Bit 1 31 1 Bit 0 30 1
DESCRIPTION Readback FS3# R e s e r ve d R e s e r ve d R e s e r ve d 3V66_3 3V66_2 3V66_1 3V66_0
Byte 5: Reserved , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
Notes:
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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5
ICS9250-37
Preliminary Product Preview
CPUCLK Buffer Configuration
Conditions Iout Vdd = nominal (3.30V) Configuration All combinations of M0, M1 and Rr shown in table below All combinations of M0, M1 and Rr shown in table below Load Nominal test load for given configuration Nominal test load for given configuration Min -7% I nominal Max +7% I nominal
Iout
Vdd = 3.30 5%
-12% I nominal +12% I nominal
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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6
ICS9250-37
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 Operating IDD3.3OP CL = 0 pF; Select @ 66M Supply Current Power Down IDD3.3PD CL = 0 pF; With input address to Vdd or GND Supply Current Input frequency Fi VDD = 3.3 V; Pin Inductance Lpin CIN Logic Inputs 1 Input Capacitance Cout Out put pin capacitance X1 & X2 pins CINX Transition Time1 Ttrans To 1st crossing of target Freq. Settling Time
1 1
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V 5 A A A 100 600 mA A MHz nH pF pF pF mS mS mS nS nS
27
7 5 6 45 3 3 3 10 10
Ts TSTAB tPZH,tPZH tPLZ,tPZH
From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 1 1
Clk Stabilization Delay
1
Guarenteed by design, not 100% tested in production.
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ICS9250-37
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDD = 3.3V RS=33, RP (pulldown)=50 (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1 2
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B2 IOL2B2 tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA
CONDITIONS
MIN 13.5 13.5 2 -27 27 175 175 45
TYP
MAX UNITS 45 45 0.4 -27 30 700 700 55 150 200 V V mA mA ps ps % ps ps
VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 20% to 80% VOH = 80% to 20% VT = 1.25 V Crossing Point VT = 1.25 V Crossing Point VT = 1.25 V Crossing Point
Guarenteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt1
1 1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP
MAX UNITS MHz 60 0.4 -23 27 4 4 55 N/A 1000 V V mA mA ns ns % ps ps
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
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ICS9250-37
Preliminary Product Preview
Electrical Characteristics - MREF/MREF_B
TA = 0 - 70C; VDD = 3.3 V 5%; CL =10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP1 1 VOH1 VOL1 IOH1 IOL1 tr1 1 tf1 1 dt1
1 1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS MHz 55 0.4 -33 38 2 2 55 N/A 250 V V mA mA ns ns % ps ps
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS MHz 55 0.4 -33 38 2 2 55 250 300 V V mA mA ns ns % ps ps
dt1
tsk11 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
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9
ICS9250-37
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
MREF MREF_BAR
CPUCLKT CPUCLKC
VCO Crystal
Notes: 1. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
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10
ICS9250-37
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9250-37 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9250-37
Preliminary Product Preview
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9250yF-37-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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12
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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